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HIP4082
Data Sheet January 3, 2006 FN3676.4
80V, 1.25A Peak Current H-Bridge FET Driver
The HIP4082 is a medium frequency, medium voltage H-Bridge N-Channel MOSFET driver IC, available in 16 lead plastic SOIC (N) and DIP packages. Specifically targeted for PWM motor control and UPS applications, bridge based designs are made simple and flexible with the HIP4082 H-bridge driver. With operation up to 80V, the device is best suited to applications of moderate power levels. Similar to the HIP4081, it has a flexible input protocol for driving every possible switch combination except those which would cause a shoot-through condition. The HIP4082's reduced drive current allows smaller packaging and it has a much wider range of programmable dead times (0.1 to 4.5s) making it ideal for switching frequencies up to 200kHz. The HIP4082 does not contain an internal charge pump, but does incorporate non-latching level-shift translation control of the upper drive circuits. This set of features and specifications is optimized for applications where size and cost are important. For applications needing higher drive capability the HIP4080A and HIP4081A are recommended.
Features
* Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations * Bootstrap Supply Max Voltage to 95VDC * Drives 1000pF Load in Free Air at 50C with Rise and Fall Times of Typically 15ns * User-Programmable Dead Time (0.1 to 4.5s) * DIS (Disable) Overrides Input Control and Refreshes Bootstrap Capacitor when Pulled Low * Input Logic Thresholds Compatible with 5V to 15V Logic Levels * Shoot-Through Protection * Undervoltage Protection * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* UPS Systems * DC Motor Controls * Full Bridge Power Supplies * Switching Power Amplifiers * Noise Cancellation Systems
Ordering Information
PART NUMBER HIP4082IB* PART TEMP. MARKING RANGE (C) HIP4082IB PACKAGE PKG. DWG. #
* Battery Powered Vehicles * Peripherals * Medium/Large Voice Coil Motors * Related Literature - TB363, Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)
-55 to +125 16 Ld SOIC (N) M16.15 -55 to +125 16 Ld SOIC (N) M16.15 (Pb-free) -55 to +125 16 Ld PDIP E16.3 E16.3
HIP4082IBZ* 4082IBZ (Note) HIP4082IP HIP4082IP
HIP4082IPZ HIP4082IPZ -55 to +125 16 Ld PDIP** (Note) (Pb-free) *Add "-T" suffix for tape and reel.
Pinout
HIP4082 (PDIP, SOIC) TOP VIEW
BHB 1 BHI 2 BLI 3 ALI 4 DEL 5 VSS 6 16 BHO 15 BHS 14 BLO 13 ALO 12 VDD 11 AHS 10 AHO 9 AHB
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/ JEDEC J STD-020. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
AHI 7 DIS 8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1995. Copyright Intersil Americas Inc. 2003-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HIP4082 Application Block Diagram
80V
12V BHO BHS BHI BLI HIP4082 ALI AHI ALO AHS AHO BLO LOAD
GND
GND
Functional Block Diagram
9 U/V BHI 2 LEVEL SHIFT DRIVER 10 AHO BHO 16 AHB BHB 1 DRIVER LEVEL SHIFT U/V
11 AHS
BHS 15
AHI
7
TURN-ON DELAY
TURN-ON DELAY
DIS
8 VDD
VDD
12
DETECTOR UNDERVOLTAGE
DRIVER TURN-ON DELAY 13 ALO BLO 14
DRIVER TURN-ON DELAY
ALI DEL BLI VSS
4 5 3 6
2
FN3676.4 January 3, 2006
HIP4082 Typical Application (PWM Mode Switching)
80V
1 BHB 12V PWM INPUT DELAY RESISTOR 2 BHI 3 BLI 4 ALI 5 DEL 6 VSS 7 AHI DIS 8 DIS
BHO 16 BHS 15 BLO 14 ALO 13 VDD 12 AHS 11 AHO 10 AHB 9 12V LOAD
FROM OPTIONAL OVERCURRENT LATCH
GND
RDIS
TO OPTIONAL CURRENT CONTROLLER OR OVERCURRENT LATCH
+
-
RSH
GND
3
FN3676.4 January 3, 2006
HIP4082
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . . . -6V (Transient) to 80V (25C to 150C) Voltage on AHS, BHS . . . . . -6V (Transient) to 70V (-55C to150C) Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Voltage on AHO, BHO . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All voltages are relative VSS unless otherwise specified.
Thermal Information
Thermal Resistance JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . See Curve Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C (For SOIC - Lead Tips Only))
Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +8.5V to +15V Voltage on VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . VAHS, BHS +7.5V to VAHS, BHS +VDD Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . -4mA to -100A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K TJ = +25C TJ = -55C TO +150C MIN MAX UNITS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION VDD Quiescent Current IDD All inputs = 0V, RDEL = 100K All inputs = 0V, RDEL = 10K VDD Operating Current IDDO f = 50kHz, no load 50kHz, no load, RDEL = 10k AHB, BHB Off Quiescent Current AHB, BHB On Quiescent Current AHB, BHB Operating Current AHS, BHS Leakage Current IAHBL, IBHBL IAHBH, IBHBH IAHBO, IBHBO IHLK AHI = BHI = 0V AHI = BHI = VDD f = 50kHz, CL = 1000pF VAHS = VBHS = 80V VAHB = VBHB = 96 VDD = Not Connected 1.2 2.2 1.5 2.5 0.5 65 .65 2.3 4.0 2.6 4.0 1.0 145 1.1 3.5 5.5 4.0 6.4 1.5 240 1.8 1.0 0.85 1.9 1.1 2.1 0.4 40 .45 4 6.0 4.2 6.6 1.6 250 2.0 mA mA mA mA mA A mA A
VDD Rising Undervoltage Threshold VDD Falling Undervoltage Threshold Undervoltage Hysteresis AHB, BHB Undervoltage Threshold INPUT PINS: ALI, BLI, AHI, BHI, & DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current TURN-ON DELAY PIN DEL Dead Time
VDDUV+ VDDUVUVHYS VHBUV Referenced to AHS & BHS
6.8 6.5 0.17 5
7.6 7.1 0.4 6.0
8.25 7.8 0.75 7
6.5 6.25 0.15 4.5
8.5 8.1 0.90 7.5
V V V V
VIL VIH
Full Operating Conditions Full Operating Conditions
2.5 -
35 -100 -
1.0 -60 +1
2.7 -150 -10
0.8
V V
-50 +10
mV A A
IIL IIH
VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions
-145 -1
TDEAD
RDEL = 100K RDEL = 10K
2.5 0.27
4.5 0.5
8.0 0.75
2.0 0.2
8.5 0.85
s s
4
FN3676.4 January 3, 2006
HIP4082
Electrical Specifications
VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K (Continued) TJ = +25C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX TJ = -55C TO +150C MIN MAX UNITS
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current VOL VDD-VOH IO + IO IOUT = 50mA IOUT = -50mA VOUT = 0V VOUT = 12V 0.65 0.7 1.1 1.0 1.4 1.3 1.1 1.2 2.5 2.3 0.5 0.5 0.85 0.75 1.2 1.3 2.75 2.5 V V A A
Switching Specifications
VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF. TJ = +25C TJ = -55C TO +150C MIN 50 MAX 70 100 100 150 25 25 80 80 100 70 2 900 350 90 125 100 3 950 UNITS ns ns ns ns ns ns ns ns ns ns ns s ns
PARAMETER Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) Rise Time Fall Time Minimum Input Pulse Width Output Pulse Response to 50 ns Input Pulse Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable Turn-on Propagation Delay (DIS - ALO & BLO) Disable Turn-on Propagation Delay (DIS- AHO & BHO) Refresh Pulse Width (ALO & BLO)
SYMBOL TLPHL THPHL TLPLH THPLH TR TF TPWIN-ON/OFF
TPWOUT
TEST CONDITIONS
MIN 50
TYP 25 55 40 75 9 9 63
MAX 50 80 85 110 20 20 -
TDISLOW TDISHIGH TDLPLH TDHPLH TREF-PW TRUTH TABLE INPUT RDEL = 10K
375
50 75 40 1.2 580
OUTPUT VHBUV X X 1 X 0 0 DIS 1 X 0 0 0 0 ALO, BLO 0 0 0 1 0 0 AHO, BHO 0 0 0 0 1 0
ALI, BLI X X 0 1 0 0 NOTE:
AHI, BHI X X X X 1 0
VDDUV X 1 0 0 0 0
X signifies that input can be either a "1" or "0".
5
FN3676.4 January 3, 2006
HIP4082 Pin Descriptions
PIN NUMBER 1 2 SYMBOL BHB BHI DESCRIPTION B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin 8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin 8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). Turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the dead time between drivers. All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. The voltage across the DEL resistor is approximately Vdd -2V. Chip negative supply, generally will be ground. A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. A High-side Output. Connect to gate of A High-side power MOSFET. A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. Positive supply to control logic and lower gate drivers. De-couple this pin to VSS (Pin 6). A Low-side Output. Connect to gate of A Low-side power MOSFET. B Low-side Output. Connect to gate of B Low-side power MOSFET. B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. B High-side Output. Connect to gate of B High-side power MOSFET.
3
BLI
4
ALI
5
DEL
6 7
VSS AHI
8
DIS
9 10 11 12 13 14 15 16
AHB AHO AHS VDD ALO BLO BHS BHO
6
FN3676.4 January 3, 2006
HIP4082 Timing Diagrams
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL DIS=0 and UV XLI THPHL
XHI
XLO
XHO
THPLH
TLPLH
TR (10% - 90%)
TF (10% - 90%)
FIGURE 1. INDEPENDENT MODE
DIS=0 and UV XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
FIGURE 2. BISTATE MODE
TDLPLH TREF-PW
TDIS
DIS or UV
XLI
XHI
XLO
XHO TDHPLH
FIGURE 3. DISABLE FUNCTION
7
FN3676.4 January 3, 2006
HIP4082 Performance Curves
3.5 IDD SUPPLY CURRENT (mA) 3.25 3 2.75 2.5 2.25 2 1.75 1.5 -60 VDD = 8V -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 VDD = 12V VDD = 10V IDD SUPPLY CURRENT (mA) VDD = 16V 16 15 VDD = 15V 14 13 12 11 10 9 8 7 6 5 4 -60 -40 -20 10kHz 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 50kHz 100kHz 200kHz
FIGURE 4. IDD SUPPLY CURRENT vs TEMPERATURE AND VDD SUPPLY VOLTAGE
FIGURE 5. VDD SUPPLY CURRENT vs TEMPERATURE AND SWITCHING FREQUENCY (1000pF LOAD)
8 LOADED, NL BIAS CURRENTS (mA) 7 6 5 4 3 2 1 0 0 50 100 FREQUENCY (kHz) 150 200 NO LOAD 1000pF LOAD PEAK GATE CURRENT (A)
1.925
2
1.75 1.5 ISRC(BIAS) 1.25 ISNK(BIAS) 1 0.75 0.815 0.5 SOURCE SINK
8 8
9
12 13 14 BIAS BIAS SUPPLY VOLTAGE (V) AT 25C
10
11
15 15
FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs FREQUENCY AND LOAD
FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS SUPPLY VOLTAGE AT 25C
1.2 1.4 NORMALIZED GATE SINK/SOURCE CURRENT (A) 1.1 -40C 1.2 VDD-VOH (V) -55C 0C
25C
1
1 125C 150C
0.9
0.8
0.6 0.8 -75 -50 -25 0 25 50 75 100 JUNCTION TEMPERATURE (C) 125 150 8 9 10 11 12 13 VDD SUPPLY VOLTAGE (V) 14 15
FIGURE 8. GATE CURRENT vs TEMPERATURE, NORMALIZED TO 25C
FIGURE 9. VDD-VOH vs BIAS VOLTAGE TEMPERATURE
8
FN3676.4 January 3, 2006
HIP4082 Performance Curves
1.4
(Continued)
8 VDD, BIAS SUPPLY VOLTAGE (V) LOWER U/V RESET 7.5 7 6.5 6 5.5 5 -60
1.2 VOL (V) -55C 1 -40C 0C 25C
LOWER U/V SET
0.8
125C 150C
UPPER U/V SET/RESET
0.6 8 9 10 11 12 13 VDD SUPPLY VOLTAGE (V) 14 15
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE (C)
120
140 160
FIGURE 10. VOL vs BIAS VOLTAGE AND TEMPERATURE
FIGURE 11. UNDERVOLTAGE TRIP VOLTAGES vs TEMPERATURE
100 DIS TO TURN-ON/OFF TIME (ns) 90 PROPAGATION DELAYS (ns) 80 70 60 50 40 30 20 -60 -40 -20 0 20 40 60 LOWER tOFF 80 100 120 140 160 UPPER tOFF LOWER tON UPPER tON
104
DISHTON 1000
100
DISHTOFF
DISLTON 10 -60 -40 -20
DISLOFF 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 160
JUNCTION TEMPERATURE (C)
FIGURE 12. UPPER LOWER TURN-ON/TURN-OFF PROPAGATION DELAY vs TEMPERATURE
FIGURE 13. UPPER/LOWER DIS(ABLE) TO TURN-ON/OFF vs TEMPERATURE (C)
2 TOTAL POWER DISSIPATION (W)
2.5
LEVEL-SHIFT CURRENT (mA)
2 16 PIN DIP 1.5 SOIC 1
1.5
1
0.5 QUIESCENT BIAS COMPONENT 0 -60 -30 0 30 60 90 AMBIENT TEMPERATURE (C) 120 150
0.5
0
20
40 60 80 SWITCHING FREQUENCY (kHz)
100
FIGURE 14. FULL BRIDGE LEVEL-SHIFT CURRENT vs FREQUENCY (kHz)
FIGURE 15. MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
9
FN3676.4 January 3, 2006
HIP4082 Performance Curves
104 VDD = 15V 85 DEAD TIME (ns) VXHS-VSS VDD = 12V 1000 VDD = 9V
(Continued)
90
80
75
100
0
10
20
30 40 50 60 70 DEAD TIME RESISTANCE (k)
80
90 100
70
100
50
0 50 TEMPERATURE (C)
100
150
FIGURE 16. DEAD-TIME vs DEL RESISTANCE AND BIAS SUPPLY (VDD) VOLTAGE
FIGURE 17. MAXIMUM OPERATING PEAK AHS/BHS VOLTAGE vs TEMPERATURE
10
FN3676.4 January 3, 2006
HIP4082 Dual-In-Line Plastic Packages (PDIP)
N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
11
FN3676.4 January 3, 2006
HIP4082 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.25 0.40 16 8 0 8 MAX 1.75 0.25 0.51 0.25 10.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 0.2284 0.0099 0.016 16 0
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 0.2440 0.0196 0.050
A1 B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN3676.4 January 3, 2006

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